Flip flops are well known in the art, as are emitter coupled logic (ECL) circuits in general. ECL circuits are often preferred due to the very high speeds achieved. ECL circuits have found particular use in telecommunications applications where increasing bit rates require increased speed of operation of logical circuits.
ECL fabrication processes are continually being upgraded in order to provide increased speed. It is also desirable to increase the speed of operation of the circuitry itself, for example to increase the toggling frequency of a D flip flop 100 shown in FIG. 1. The toggle rate, f.sub.toggle, is the inverse of the sum of the setup time for data input D.sub.M 102 and the propagation delay for clock input CLK 101 to reach output Q 103, ##EQU1##
FIG. 2 is a prior art logic diagram of the typical D flip flop 100 of FIG. 1, including input port 102 for input data D.sub.M and input port 101 for input clock signal CLK. Flip flop 100 also includes output port 103 and 104 for providing output signals Q and Q, respectively, in response to input signals D.sub.M and CLK. The logic diagram in FIG. 2, shows that flip flop 100 may be constructed of a combination of NAND logic gates or OR logic gates, such as OR gate 10 or NAND gate 20 shown in FIG. 3.
The logical operation of NAND gate 20 and OR gate 10 (shown in FIG. 3) is functionally equivalent as is described in Table 1.
Table 1 ______________________________________ A .sup.-- A B .sup.-- B Z .sup.-- A + .sup.-- B AB ______________________________________ 0 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0 0 ______________________________________
Table 1 illustrates that output Z may be expressed as EQU Z=AB (2)
or, equivalently, as EQU Z=A+B (3)
FIG. 4 is a typical prior art ECL circuit representation of NAND gate 20, or OR gate 10. ECL circuit 200 is referred to as a two level ECL circuit, since a first and a second level bias reference signal, VBB1 and VBB2 are implemented. VBB1 is typically equivalent to the voltage level at the midswing of an ECL input signal voltage range such that the logic state of an ECL input signal may be easily determined when compared to VBB1. The voltage level of VBB2 may be expressed as EQU VBB2=VBB1-Vbe (4)
where Vbe is equivalent to one base-to-emitter voltage drop through a transistor, or approximately -0.8 V. For example, if the ECL input signal voltage swing is from -0.75 V (equivalent to a logical one) to -1.8 V (equivalent to a logical zero), VBB1 is typically equivalent to -1.3 V, while VBB2 is typically -2.1 V. Thus, if the input voltage of ECL input data signal A provided to the base of transistor 209 is a logical one, or -0.75 V, which is a voltage greater than VBB1, transistor 209 turns on, or biases to conducting, while transistor 210 turns off. Conversely, if ECL input data signal A is a logical zero, or -1.8 V, transistor 209 turns off, while transistor 210 switches on.
In the prior art ECL NAND gate 200, an extra transistor 208 is needed in the signal path of ECL input signal B to the base of the differential pair transistors 207/217, referenced to a second level bias reference voltage VBB2. Since VBB2 is approximately -2.1 V, or approximately at a voltage at the midswing of an ECL input signal reduced by Vbe, transistor 208 is necessary to reduce ECL input signal B by Vbe to properly reference input signal B to VBB2. Prior art NAND circuit design of FIG. 4 has a drawback of increasing the propagation delay between ECL input signal B to output signal Z due to the extra transistor propagation delay required to reduce input signal B voltage for a second level bias reference, VBB2. As illustrated in FIG. 4, input signal B must first propagate through transistor 208 prior to reaching the base of transistor 207. The propagation delay from input signal B to output signal Z is therefore longer than from input signal A to output signal Z, or EQU t.sub.pd A to Z&lt;t.sub.pd B to Z (5)
Input signal B has a longer propagation delay due to input signal B propagating through transistors 208, prior to propagating through the differential pair of transistors 207/217 and transistor 212, while data input signal A need only propagate through differential pair of transistors 209/210 and transistor 212.
FIG. 5 is an example of a typical prior art ECL circuit representation of flip flop 100 implementing one or more of the prior art ECL NAND gate circuit 200. The logical operation of the prior art ECL flip flop 300 circuit is depicted in Table 2. Flip flop 300 receives a data input signal D.sub.M-1 on input lead 302 and a clock signal on input lead 301 and, in response thereto, provides output signals Q and Q on output leads 303 and 304, respectively. ECL flip flop 300 includes master subcircuit 300-M, and slave subcircuit 300-S. Nodes N3 and N4 serve as the output nodes of master subcircuit 300-M, as the input nodes of slave subcircuit 300-S. The master and slave subcircuits each operate in the transparent mode, wherein master and slave input data D.sub.M and D.sub.S immediately appears at the master and slave outputs, respectively, or the latch mode, in which previous input data D.sub.M-1 and D.sub.S-1 is latched and provided at the output. When master subcircuit 300-M is in the transparent mode, slave subcircuit 300-S is in the latch mode, and vice versa.
When the clock input signal applied to lead 301 is low, master flip flop 300-M operates in the transparent mode, providing input signal D.sub.M as its intermediate output signal on nodes N3 and N4 which, in turn, provide the data input signal D.sub.S to slave flip flop 300-S. At the same time, slave flip flop 300 operates in the latch mode, providing Q and Q output signals indicative of the previous data value D.sub.S-1 applied to slave flip flop 300-S.
Conversely, when the clock signal applied to input lead 301 is high, master flip flop 300-M operates in the latch mode, and applies a signal D.sub.S to slave flip flop 300-S which is indicative of the previous input data of D.sub.M-1 applied to master flip flop 300-M. At this time, with a high clock signal, slave flip flop 300-S operates in the transparent mode, providing Q and Q output signals indicative of this D.sub.S data provided by master flip flop 300-M.
A current source bias voltage V.sub.CS is applied to the base of transistor 372, thereby causing transistor 372 to serve as a current source. Transistor pair 326/333 forms a differential pair responsive to the clock input signal applied to lead 301. The base of transistor 333 is connected to receive a bias voltage VBB2 such that for a high clock input signal applied to lead 301, transistor 326 turns on (and transistor 333 turns off), thereby enabling latch mode differential pair 324/325 and disabling transparent mode differential pair 329/330 of master flip flop 300-M. Conversely, for a low clock input signal on lead 301, transistor 326 turns off (and transistor 333 turns on), thereby enabling transparent mode differential pair 329/330 and disabling latch mode differential pair 324/325 of master flip flop 300-M.
Transistors 329 and 330 form a differential pair of transistors, with the base of transistor 330 receiving bias voltage VBB1 and base 302 of transistor 329 receiving the D.sub.M input signal. With a logical one D.sub.M input signal applied to lead 302, and transistor 333 conducting due to a low clock input signal applied to lead 301, transistor 329 turns on, thus causing transistor 331 to be biased to a low state of conduction, and biasing transistor 332 to a high state of conduction. This establishes suitable voltages at nodes N3 and N4 which are applied to the bases of differential transistor pair 324/325 which latch the D.sub.M input data when transistor 326 turns on in response to a high clock signal subsequently applied to lead 301.
The voltages on nodes N1 and N2 control the conduction states of transistors 332 and 331, and thus the voltages on nodes N3 and N4, respectively. The voltages on nodes N3 and N4 provide the output signal from master subcircuit 300-M which are applied to latch mode differential pair 324/325, and transparent mode differential pair 338/339 of slave subcircuit 300-S. The output signals on nodes N3 and N4 are controlled by the input data D.sub.M when master flip flop 300-M operates in the transparent mode (low clock signal) and by the latched value of the previous data input signal D.sub.M-1 stored in latch 324/325 when master flip flop 300-M operates in the latch mode (high clock signal).
Slave flip flop 300-S operates in much the same manner as master flip flop 300-M, as indicated in Table 2.
In a master-slave flip flop such as flip flop 300 of FIG. 5, there are two propagation delays which are of primary concern. The set-up time is defined as the time required for the data input signal D.sub.M applied to input lead 302 of master flip flop 300-M to propagate through master flip flop 300-M and to provide on nodes N3 and N4 data input signal D.sub.S to slave flip flop 300-S. As shown in the schematic diagram of FIG. 5, the input data D.sub.M set-up time is equivalent to the propagation delay through transistors: 324/325 and 331/332.
The other propagation delay of importance is referred to as the clock to Q output propagation delay. This is time required for the D.sub.S data to appear as output data in response to a low clock signal. As seen in FIG. 5, the propagation delay associated with the clock to Q output delay is that associated with the following transistors: 320; 340/343; and 346/347. Thus in the prior art ECL flip flop circuit, EQU t.sub.pd data to Q&lt;t.sub.pd clock to Q (6)
Although the prior art ECL flip flop circuit of FIG. 5 functions properly, the electronics circuits coupled to the ECL flip flop circuits are continuously being improved to operate at a faster and faster speed. To avoid slowing down the operation of the electronic circuits to which the ECL flip flop is coupled, ECL flip flop circuits must also be continuously improved to operate at a faster speed. Accordingly, it remains desirable to provide an ECL flip flop with even greater speeds.